RISC-V News Roundup: March 20, 2026

Other technical issues RISC-V
1

:penguin: Kernel & Toolchain

  1. Linux 7.1 to Support HDMI on Lichee Pi 4A
  • Summary: The Linux 7.1 kernel will add HDMI display support for the Lichee Pi 4A via device tree patches, enhancing the multimedia capabilities of this RISC-V development board.
  • Timestamp: 2026-03-19 18:13
  • View Original
  1. RISC-V IOMMU Driver Fixes Signedness Issue
  • Summary: A kernel patch resolves a signedness bug in the RISC-V IOMMU platform driver related to IRQ counting, preventing incorrect error checks caused by writing negative error codes into unsigned fields.
  • Timestamp: 2026-03-20 02:26
  • View Original
  1. RISC-V Kernel Fixes GPIO Interrupt Unit Definition for Microchip PolarFire SoC
  • Summary: A RISC-V kernel patch corrects the #interrupt-cells value for the GPIO controller in the Microchip PolarFire SoC device tree from 1 to 2, aligning with variable interrupt types and multi-interrupt line design, improving interrupt description accuracy on platforms like the Icicle Kit.
  • Timestamp: 2026-03-20 00:31
  • View Original
  1. Minor Device Tree Improvements for BeagleV-Fire (Patch Set)
  • Summary: Conor Dooley submitted five RISC-V device tree patches for the Microchip BeagleV-Fire, fixing GPIO interrupt unit definitions, cleaning up nodes and naming conventions, and adding ADC interrupt information to improve board support in the mainline kernel.
  • Timestamp: 2026-03-20 00:31
  • View Original
  1. [PATCH] Andes Platform Uses SBI PMA for Non-Cacheable Memory Management
  • Summary: The Andes RISC-V platform implements non-cacheable memory region management via the SBI PMA interface, enhancing U-Boot’s control over physical memory attributes.
  • Timestamp: 2026-03-19 16:37
  • View Original

:hammer_and_wrench: Hardware & Chips

  1. TUMCREATE Leading Development of Open-Source Post-Quantum Secure RISC-V Processor
  • Summary: TUMCREATE is leading the development of an open-source post-quantum secure RISC-V processor, aiming to strengthen hardware security against future cryptographic threats and advance research and ecosystem growth in this domain.
  • Timestamp: 2026-03-19 23:22
  • View Original
  1. CoreLab’s Allen Wu on Reducing Custom AI Chip Costs
  • Summary: CoreLab Technology explores leveraging the RISC-V architecture to reduce costs in custom AI chip design, driving innovation in AI hardware.
  • Timestamp: 2026-03-19 14:11
  • View Original