RISC-V News Brief: March 19, 2026

Other technical issues RISC-V
1

:penguin: Kernel & Toolchain

  1. Linux 7.0 Released: RISC-V and Other Architectures Receive Updates

    • Summary: Linux 7.0 has been officially released, featuring improvements across multiple architectures including Intel, AMD, ARM, and RISC-V. For RISC-V, such major version updates typically mean expanded platform support, enhanced driver maturity, and the inclusion of architecture-specific features in the mainline kernel—boosting ecosystem compatibility and upstream availability. Specific RISC-V changes are not yet disclosed; details will be confirmed in the official kernel release notes and merge logs.
    • 时效: 2026-03-18 19:41
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  2. RISC-V KVM: Batch TLB Flush Patch v2

    • Summary: This patch optimizes the TLB flush mechanism in RISC-V KVM when modifying second-level page table entries by batching operations, reducing software overhead. It significantly improves performance, especially in dirty page tracking scenarios, with reduced execution time and lower lock contention. Verified on QEMU 10.2.1.
    • 时效: 2026-03-18 20:37
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  3. [PATCH v3] Fix RISC-V KVM Large Page Write Protection Loss

    • Summary: Submitted by Wang Yechao, this patch fixes the write protection failure for large pages (2M/1G) in RISC-V KVM during dirty page logging, ensuring correct protection regardless of page chunk size. The patch has been reviewed and will be merged into the Linux kernel mainline.
    • 时效: 2026-03-19 00:28
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  4. RISC-V KVM: Fix Double-Free in PMU Snapshot Shared Memory

    • Summary: A RISC-V KVM patch resolves a double-free issue in kvm_pmu_clear_snapshot_area(): when kvm_vcpu_write_guest() fails within kvm_riscv_vcpu_pmu_snapshot_set_shmem(), sdata is freed but not nullified, causing a second release during vCPU destruction and triggering a KASAN report. The fix eliminates the double-free risk by avoiding dangling pointers (e.g., setting to NULL after freeing). This is a bug fix that enhances stability and debuggability of the KVM PMU snapshot path.
    • 时效: 2026-03-18 17:30
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  5. Fix RISC-V APLIC Interrupt Controller Duplicate Registration

    • Summary: This patch resolves a kernel crash caused by duplicate registration of syscore operations for the RISC-V APLIC interrupt controller in multi-NUMA node environments. The patch has been submitted and is under review, representing a driver-layer fix in the Linux kernel.
    • 时效: 2026-03-19 00:28
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  6. Microchip Polarfire SoC GPIO Interrupt Binding Fix

    • Summary: Conor Dooley submitted a device tree binding patch for the Microchip Polarfire SoC, correcting the erroneous hierarchy between the GPIO controller and PLIC. A dedicated multiplexer device was introduced to accurately describe the mapping of 70 GPIO interrupts. This improves interrupt handling accuracy and lays the foundation for future driver support. The patch is currently in kernel patch review.
    • 时效: 2026-03-18 19:05
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  7. RISC-V Spacemit K1 Device Tree PHY Node Reordering Patch

    • Summary: This patch reorders the USB and PCIe PHY nodes in the Spacemit K1 SoC device tree to align with register addresses, improving readability and maintainability. No functional changes—this is purely a structural optimization. Submitted and signed off by developer Chukun Pan.
    • 时效: 2026-03-18 18:01
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:hammer_and_wrench: Hardware & Chips

  1. Zhuhai Deploys RISC-V Server Cluster

    • Summary: The “Cloud City” project in Zhuhai has successfully deployed a RISC-V architecture server cluster to support smart city applications, marking the first large-scale commercial RISC-V data center deployment with significant demonstration value.
    • 时效: 2026-03-18 12:42
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  2. Designing Modular, Reusable RISC-V SoCs with Topwrap and Guineveer

    • Summary: CHIPS Alliance has launched the toolchain Topwrap and Guineveer, aimed at simplifying modular RISC-V SoC design and reuse. This solution boosts development efficiency and lowers the barrier to custom chip design, currently in open-source promotion phase.
    • 时效: 2026-03-19 08:33
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  3. Yiswei Computing Pushes IPO Amid Massive Losses, Doubling Down on RISC-V

    • Summary: Despite massive losses, Yiswei Computing continues advancing its IPO process, with RISC-V-related initiatives as one of its key strategic directions. This reflects the tension between RISC-V’s narrative in capital markets and real-world industrial deployment. The critical factors moving forward are the use of proceeds, product roadmap, and verifiable customer adoption.
    • 时效: 2026-03-18 10:15
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:busts_in_silhouette: Community & Industry

  1. Lanxin Computing Secures Hundreds of Millions in Funding; Founder Previously Led ByteDance Server Chip Team
    • Summary: RISC-V chip company Lanxin Computing has raised hundreds of millions in funding. Its founder previously led the server chip team at ByteDance, highlighting sustained capital interest in Chinese RISC-V startups. The company is currently in early development, with no public product roadmap yet.
    • 时效: 2026-03-18 18:52
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